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 Home > Achievement > Main Contributions > SCI > Design of a High Efficiency DC-DC Buck Converter With Two-Step Digital PWM and Low Power Self-Tracking Zero Current Detector for IoT Applications

Domestic/International 국외  Principal Author Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee 
Title Design of a High Efficiency DC-DC Buck Converter With Two-Step Digital PWM and Low Power Self-Tracking Zero Current Detector for IoT Applications 
Journal IEEE Transactions on Power Electronics (Impact Factor : 6.373 ; JCR 상위 10%) 
Authors SangYun Kim, Young-Jun Park, Ali. Imran, Truong Nga, Ho-Cheol RyuZaffar Khan, Seong-Mun Park, YoungGun Pu, Minjae LeeKeum Cheol Hwang, Youngoo Yang and Kang-Yoon Lee 
Date 2018년 2월 Page 1428 - 1438 
Volume 33   Number 2 

In this paper, a high efficiency dc–dc buck converter with two-step digital pulse width modulation (DPWM) and low power self-tracking zero current detector (ST-ZCD) is proposed for Internet of Things (IoT) and ultralow power applications. The hybrid DPWM core with high linearity and low power consumption is proposed to implement the high efficiency DPWM dc–dc converter. It is composed of a two-step delay control using the counter and delay line. An adaptive window analog to digital converter is proposed to reduce the output voltage ripple within 20 mV. A dead time generator is implemented with the proposed ST-ZCD to minimize the reverse current. The ST-ZCD can improve efficiency by reducing the control loss that accounts for a large proportion of the dc–dc converter. Also, all digital typeIII compensator is implemented for the low power and small die area. This chip is fabricated with a 55 nm CMOS process, which uses the standard supply voltage of 1.5–3 V to generate the output voltage of 1.2 V. The total active area is 500 µm × 300 µm. The measured peak efficiency of the DPWM dc–dc buck converter is 91.5% with a quiescent current consuming only 130 µA.

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